At the recently concluded AMD Next Horizon event, AMD unveiled details about their upcoming AMD EPYC “Rome” processors and 7nm Vega GPUs. The first revelation is the shift from 32 cores in existing EPYC processors to 64 cores thanks to 7nm manufacturing process which delivers a 2x improvement in transistor density compared to 14nm nodes.
AMD took this opportunity to introduce a new design which utilizes a new I/O die design which has CPU core chiplets which is separated from the I/O functionality and having the CPU cores in their own separate dies.
Zen 2 processors will have a 14nm I/O die in the center that houses 8 memory controllers along with infinity fabric interconnects which are linked to the CPU chiplets. The chiplets themselves are 7nm and each will contain 8 Zen 2 CPU cores along with a set of PCIe lanes. Even though the memory controllers are in the I/O dies, the PCIe lanes will remain attached to the CPU core.
The advantage of the I/O die is that it will allow each CPU chiplet to have equal access to the memory controllers. The configuration of current EPYC CPUs has their own memory controller in each die that means if one core needs memory attached to a different controller in a different die, there could be latency penalties to access that memory compared to accessing memory that is sitting in it’s own die.
But with the I/O die in the next generation EPYC, these latency penalty should be eliminated and each CPU chiplet will have equal access latency to the overall memory pool. Though we don’t have much details on how this works, AMD states that there is an improvement in memory latency with this new I/O die implementation.
With this new I/O design, AMD can now easily scale up EPYC processors compared from having just 4 die configurations like the previous generations of CPUs. With that, the new “Rome” processors can have up to 8 CPU chiplet dies which will contain 8 Zen 2 CPU cores each for a total of 64 cores in the top end “Rome” processor.
THe benefit of using smaller 8 core Zen 2 dies on 7nm apart from being able to increase core count is that it will be more efficient to manufacture as smaller chips are easier to make.
The new AMD EPYC Rome processor will support up to 4TB of DRAM per socket and a total of 128 PCIe 4.0 lanes. All these new design features allows the next generation AMD EPYC provide 2x more performance per socket and 4x floating point performance per socket.
Although AMD hasn’t revealed any further details like the clock speed, power consumption or any IPC figures, going from 32 cores to 64 cores per socket is a huge improvement where datacenters will definitely benefit from that kind of processing density.
The new 7nm node allows 2x more transistor density, and will provide the same performance at half the power, or 1.25x more performance in the same power in both their next generation CPU and GPUs according to their presentation.
AMD also revealed their 7nm Vega GPU but for now it will only be in the form of Radeon Instinct MI60 and MI50.
Though Vega 20 on 7nm still uses the same GPU design as the Vega 10 on 14nm, it has 64 compute units and uses HBM2 memory. The Vega 20 has improved double precision capabilities which will largely benefit compute applications. The Vega 20 will also have a second pair of HBM2 controller which allow it to support up to 32GB of memory, increased clockspeeds of 2GB/s, as well as support for PCIe 4.0. The new GPUs can also use infinity fabric links for direct connections with other Radeon Instinct cards.
In terms of performance, again, AMD hasn’t revealed any specific details like clock speeds but they did mention in their presentation that 14.7TFlops of FP32 performance that’s around 1.5x performance gain compared to the 14nm GPU in the same power consumption. For compute workloads, the real benefit is the improvement in FP32 and FP64, and higher memory capacity and higher memory bandwidth.
The AMD EPYC “Rome” is now sampling to customers and will be launched in 2019 though there is no exact mention when during the presentation. The Radeon Instinct MI60 will be shipping on Q4 this year and the MI50 will be available on Q1 next year.
So how is all of this going to translate when AMD brings these new technology into their consumer grade products like the much anticipated Ryzen 3000 series and the upcoming Navi gaming cards?
Right now we can go as far as to speculate. With the improvements in the 7nm process which allows more performance gains at the same power as the 14nm definitely says a lot. Presumably, AMD will be able to deliver higher clock speeds in 7nm as what they have shown in relative performance gains from 14nm and 12nm. The new I/O die design can also allow AMD to pack more CPU cores in the processors with the use of the CPU chiplets. Presumably, this will allow future consumer Ryzen products to have double the core count of what we have right now with the Ryzen 7 2700x in the AM4 platform and Threadripper 2990WX with the TR4.
As for the consumer gaming GPUs, unfortunately, the 7nm Vega isn’t Navi but with the improvements of the 7nm process for the GPU, hopefully this will help close the gap in terms of architectural constraints that Vega GPUs had considering that the Nvidia GeForce RTX 2080ti right now is much more powerful than the Vega 64. Although we cannot totally say that the 7nm process alone can help Navi close the gap with Nvidia’s Turing architecture, AMD would really need to catch up in terms of improving their GPU architecture for gaming.